1. Field of the Invention
The present invention is generally related to digital data storage elements and more particularly relates to digital data storage elements having a plurality of access ports.
2. Description of the Prior Art
The application of digital data storage to digital computation has been known for some time. As new and more powerful data processing hardware has been developed, corresponding improvements to memory technology have also occurred. However, the bandpass of memories has historically been a limiting factor on processing speed. Some of the improvements to memory systems involve enhancement to memory access time and memory cycle time directly. These techniques are concerned with the nature and characteristics of the individual storage elements themselves.
Effective memory bandpass has also been improved by system level, architectural changes. In the most basic terms, these approaches tend to focus on the arrangement of sequential and block memory locations. Interleaving of addressing from separate memory elements and overlapping of instruction and operand fetches to different memory elements have improved system level memory performance. With certain modern processor architectures, however, many instructions require two operands, which typically necessitates two serial accesses to memory. This produces up to 100% access penalty with normal overlap techniques, whereas an overlap design to optimize these accesses tends to be very complex.
A somewhat more recent development utilizes hierarchical memory systems of differing sizes and cycle times. The now popular use of cache memories falls within this category of improvement. Currently, many data processing systems use cache memories for performance enhancement.
Quite recently, system performance has been enhanced through the use of multiple port memories. The desirability of such a multiple port memory may be seen in "Computer Engineering Handbook", McGraw-Hill, Inc., edited by C. H. Chen, 1992, at pages 14.8-14.9. Even though this reference certainly does not provide an enabling disclosure, it does suggest system performance enhancement using multiple port memory elements. In constructing an actual multiple port memory, however, it is likely that the complete symmetry suggested by Chen is neither necessary nor desirable as explained below.
In multiple port memories, the effective pass band is improved by permitting more than one access to a single memory element. U.S. Pat. No. 4,937,781, issued to Lee et al. is an example of an early technique in which an arbitrator-selects one of two ports requesting access. Though this type of structure permits access by only one port at a time, overlapping of certain of the accessing functions does provide some performance enhancement.
An improvement to the multiport memory is found in U.S. Pat. No. 4,991,138, issued to Cavaliere et al. In its preferred mode, this technique uses a dual port memory in which some bunt all of the dual port functions may be overlapped in time. A further improvement is found in U.S. Pat. No. 5,124,950, issued to Fukushi et al. In this approach, a two port memory is implemented wherein a first port can read and a second port can write simultaneously. An error signal is generated whenever a simultaneous read and write access are attempted at the same memory cell. U.S. Pat. No. 5,111,431, issued to Garde provides two write ports and one read port. The two ports of a dual port memory are utilized for error detection in U.S. Pat. No. 5,142,540, issued to Glasser.